module IDDR_rtl (
    input               C ,
    // input               CB ,
    input               R ,

    input               D ,
    output  reg         Q1 ,
    output  reg         Q2
) ;

    always @(posedge C or posedge R) begin
        if(R)
            Q1 <= 1'b0 ;
        else 
            Q1 <= D ;
    end
    always @(negedge C or posedge R) begin
        if(R)
            Q2 <= 1'b0 ;
        else 
            Q2 <= D ;
    end

endmodule

